The semiconductor industry has experienced rapid growth. The manufacturing of a field-effect transistor (FET) is focusing on the scaling down of the dimensions of the FET to improve the packing density of the semiconductor device. However, physical constraints in achieving ultra-small dimensions in the classical planar transistor led to the development of a non-planar transistor. At present, a gate-all-around (GAA) FET has been developed, and considered as one of the next generation non-planar transistors with ultra-small dimensions and a good short-channel effect (SCE).
A vertical FET is one of the GAA FET, which the source-drain current flows in a direction perpendicular to the substrate surface. The vertical FET applies a plurality of semiconductor nanowires each surrounded by gate electrode as the channel between a source electrode and a drain electrode. However, there are difficulties in improving the packing density of the semiconductor device because of the limitations in current manufacturing technology.